Resume of Embedded Developer

Title
Embedded Developer

Primary Skills
uProc development

Location
US-NC-Cary

Posted
Dec-10-07



Career Objective

Embedded development.
Skills

Programming Languages: C, C++,C#, Tensilica/Intel/AMD/PPC/ARM/MIPS Assembler
Operating Systems: Windows/Linux/Unix, Embedded RTOS's
Architectures: ARM, AVR,Tensilica, Intel, PowerPC, StrongARM, MIPS, SH and S/390

Professional Experience

IBM Systems&Technology Group,RTP, NC
xSeries & RSS Server Engineering
Contracted to design, develop and test HW/SW components involving technically demanding projects which covered chipset technology from companies including Intel, AMD, LSI, VIA and Renesas. Reviewed and advised on all aspects of manufacturing, reliability, serviceability and availability for the STG division.

Atmel Technical Resource, ARM Core based Microcontrollers, NC 2002-2006
-Director of USA/Canada application support for the ARM7/9 product family. Provided technical sales, technical marketing and technical training to corporate FAE's, and distributors FAE's. Developed SW projects for the various evaluation boards, tool chains and OS's. Authored App Notes and FAQ's to resolve key customer issues. Provided hands on customer support to resolve any technical issues. Directed third party application issues until a workable solution was provided. Coordinated failure analysis between the customer and factory. Furnished technical support on ARM based ASIC's.
-FAE AVR based Microcontrollers
Software development for several key customers

TranSwitch Principal Member of Technical Staff, RTP, NC 1999-2002
TranSwitch Corp. is a leading developer and global supplier of semiconductor solutions that serve the Worldwide Public Network Infrastructure, the Internet infrastructure and corporate Wide Area Networks(WANS).
-Project Leader in the Advance Technology Center. The ATC's charter was to set corporate directions which involved evaluating and selecting external Intellectual Property(IP) or Procedures. Corporate roll outs included a system on a chip(SOC) methodology, IP Reuse, OCP system bus(SONIC) and reconfigurable processors.
Corporate transformations included switching from an internal MIPS like processor to Tensilica's XTENSA processor and tool set. This switch also led to adopting the ATI RTOS as a standard. Typical SOC's contained multiple processors with customized OP's and as many as twenty-four other IP blocks.

IBM Technical Lead on First PPCE Core, RTP, NC 1998-1999
-Developed, designed and verified the execution, instruction, data cache and instruction cache units for a new superscaler embedded microprocessor. The design, which will be incorporated into the ASIC library, will provide SOC designers a high performance, high frequency, small die size, low power and low cost solution to their design needs. An open architecture was implemented to provide, depending on customer requirements, MAC, DSP, and FP units. Developed and implemented a verification environment and tools new to the PPCE test methodology. The objective was to reduce the verification cycle while providing additional coverage based on previous designs. This involved extensive cycle accurate C models and C based stimulus generator. To cover specific code sequences an assembler type of instruction set was developed.

IBM Technical Lead - Embedded Processor Performance, RTP, NC 1996-1998
-Developed RTP's embedded benchmark suite. This suite specifically targeted applications that covered the embedded processor market. The embedded processor systems that were under study included the SA110, ARM7, i960, MIPS 4300, MIPS 5000, SH3, PPC401, PPC403, PPC603, PPC740 and the PPC750. Other factors that were taken into account while studying performance involved several vender compilers, OS's, code density, power requirements and debug environments.

IBM X86/PPC Processor Performance Engineer, Burlington, VT 1996-1996
-Developed Burlington's superscaler/superpipelined micro-processor performance
verification methodology. Maximized processor performance by writing analysis tools, which would identify software hot spots and hardware bottlenecks. Carried out micro-architectural trade-off experiments, analyzing results, and proposed solutions for optimal silicon implementation. Pre/post silicon platforms were involved for both x86 and PPC architectures.

CISC/RISC Microprocessor Development, Burlington, VT 1994-1996
-Responsible for the architectural/logic function verification of the dispatch unit, memory management unit, and bus interface unit. Focus covered both Uni/Multi-processor environments for a hybrid x86/PPC processor. Developed the software drivers to emulate and irritate interfaces, and the behaviorals to check for functionality, protocol, and performance. The testbenches covered memory coherency, address translation, exceptions, interrupts, snooping, load/store conflicts, store forwarding, writeback, mispredicted branches, and self-modifying code. The testbenches improved verification performance by targeting smaller models.
-Wrote a library of MASM testcases covering virtual, protected, and real modes to verify Pentium compatibility.

IBM CMOS CISC Microprocessor Design, Poughkeepsie, NY 1992-1994
-Functional design verification team leader. Responsible for staffing and establishing schedules for the verification of the hardware against its logical model to meet project requirements. Designed and implemented a Cache randomizer and logic simulator in C/C++ and PL/1. The code provided a modeling framework for functional verification of designs. This included tracking for all physical and logical model dependencies to ensure completeness of test. Provided a hierarchical database to ensure that the simulation and modeling stayed in sync while the design progressed.

IBM ES/9000 Mainframe Family, Poughkeepsie, NY 1987-1992
-Responsible for the overall design of the CPU Cache controller. Designed ASICs and TCMs for the cache/buffer control element. Hardware timing, ASTAP, and L/P checking coordinator. Coded simulation testcases using PL1/REXX to cover all scenarios for a L1 Data Cache and L1 Instruction Cache. Testing included out-of-order multiple pipeline execution, address translation, cache set associativity, LRU management, delete bits, ECC, and recovery to cover S/390 Architecture.

IBM Various Staff Engineering Positions, Poughkeepsie, NY 1978-1987
-Created processor models and researched benchmark findings, which were used to define the optimal hardware implementation of the ES/9000 processor, based on a given technology. Provided subsystem and system hardware bringup and clock stress testing. Wrote test cases and assembler code test loops to functionally stress arrays and logic. Performed critical path analysis using the APL Delay Calculator.

Education
B.S. Electrical Engineering 1978 GPA 3.5/4.0
Polytechnic University of New York
Special Honors ETA Kappa Nu

Certifications
See above


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