Device Engineer Resume

Title
Device Engineer

Primary Skills
CMOS Process Integration and Device Engineering

Location
US-DC-Washington (will consider relocating)

Posted
Apr-11-09

Objective: Obtain a challenging semiconductor device engineering, process integration or technology transfer position.

Education: Rochester Institute of Technology: M.E. Microelectronic Engineering, 9/93 -- 9/94. GPA 3.9/4.0

University of Texas at Austin: B.S. Electrical Engineering -- Electronic Materials and Devices, 1/89 -- 8/91. GPA 3.0/4.0

Expertise: 14 years DRAM and logic process integration, process transfer and fab startup experience in US, Taiwan and Germany. Proficient at writing and analyzing DOEs, analyzing inline process, defectivity, electrical parametric and yield data. Expertise with utilizing Six Sigma methods to problem solving and creating, implementing FMEAs and project management. US citizen and willing to relocate.

Experience:
Development Engineer, Qimonda: 48nm DRAM overall process integration
300mm development fab. Dresden, Germany 09/07 -- 02/09

Coordinated development and integration activities between integration module owners for 48nm 4F2 generation buried wordline DRAM technology.
Led unit process engineering, device engineering, yield enhancement or product engineering teams to resolve defectivity, parametric (discrete device electrical data) and yield issues (functional test).
Initiated brainstorming and problem solving sessions to resolve process and integration roadblocks.

Staff Engineer, Qimonda: 90nm/80nm DRAM Deep Trench process integration
300mm production fab, Richmond, VA. 10/02 -- 09/07.

Deep trench integration module owner of 80 and 90nm process nodes.
Implemented development fab process changes to production fab.
Initiated process simplification, yield enhancement and process improvement changes with support from unit process and product engineering groups.
300mm fab startup as deep trench module expert and supported other integration modules during startup phase (first silicon run).
.
Senior Engineer, Infineon: 0.2um to 140nm DRAM process integration roles
200mm production fab, Richmond, VA. 09/99 -- 10/02.

Active area module owner implemented process improvements, yield enhancement and process simplification by leading multi-functional teams with unit process, defect reduction and product engineering participation.
Gate conductor module owner worked with unit process, defect reduction and product engineering to implement process improvements and yield enhancement activities. Analyzed parametric data and ran experiments to vary and target transistor thresholds. DRAM integration training class presentations.

Engineer, WaferTech: 0.35um 6T SRAM technology process integration
200m production fab, Camas, WA. 12/97 -- 8/99

Supported process transfer of 0.25um, 4 layer metal logic technology from Taiwanese fab to US production fab during startup phase (first silicon run).
0.35um 6T SRAM process integration owner -- implemented process improvements, simplification and yield improvement changes.

Engineer, Siemens: 0.35um Deep Trench DRAM technology transfer
200mm development/production. East Fishkill, NY -- Hsinchu, Taiwan. 9/96-11/97

Coordinated startup wafer efforts of 0.35um DT DRAM technology transfer from IBM East Fishkill development fab to PROMOS Taiwanese production fab.
Back End of Line module owner during startup phase at Taiwanese JV fab.

Engineer, Motorola: 0.65 and 0.5um Logic process integration
200mm production fab, Austin, TX 9/94 -- 9/96.

Initiated yield enhancement activities between defect reduction and unit process engineering.
Process of record, fab disposition and yield responsibilities for 0.65um CMOS dual layer metal microprocessor product line.

R.I.T. Microelectronic Student Factory; NMOS and CMOS device processing and characterization. 9/93 -- 5/94.

IT support, Trucks-For-You: Assisted administration of Novell LAN, managed and designed foxpro databases and general office software support. 9/91 -- 7/93.

Assistant Engineer, Tensleep Design: Built customized Cadence CAD library, help pay for school expenses. 4/91 -- 5/91.

Grader, University of Texas EE Dept.: Graded homework papers for Electronics I and II, lecturer Dr. Ian Thomas, help pay for school expenses. 6/90 -- 5/91.

Skills: Proficient in MS Office, JMP, Lotus Notes. Promis, Workstream and Profab wip systems. Basic SAS and VBE programming skills. Space and Datalog SPC systems proficient. Using Six Sigma methods for problem solving and creating FMEAs.


References available on request

Certifications
See above


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