Resume of Verification & Development Engineer

Title
Verification & Development Engineer

Primary Skills
Verification and Testing

Location
US-CA-

Posted
Feb-05-08


OBJECTIVE Seeking a challenging engineering position in Design Verification or Methodology Development.


PROFESSIONAL SUMMARY

Excellent knowledge of reading schematics, drafting, analyzing, debugging, and verifying data.

Excellent knowledge of Verilog, VHDL, and Mixed-Language (Verilog/VHDL) , Perl, Unix, Shell scripts, Matlab, and MS Office.

Simulators: ModelSim (VHDL & Verilog), VCS (Synopsys), and Verilog-XL, NC-Verilog (Cadence), Icarus. Synopsys' Design Analyzer, SignalScan.

PROFESSIONAL EDUCATION

EDUCATION MBA/Tech. Management & Accounting (U. of Phoenix: Jan 2007 -- Present).

BS in Electrical Engineer (Florida A&M University: Aug -- 1997).
MS in Electrical Engineer (San Jose State University: Aug -- 1999).

COURSES Analysis and Design of Analog Integrated Circuits, Principles of CMOS VLSI Design, Digital Design in VHDL, Advanced Logic Design, Verilog & Synthesis, Digital Integrated Circuit Design, Functional Verification of HDL Models, Structured Logic Design with VHDL.

CERTIFICATES LSI Flexstream 3.0, LSI Floor Plan Design, Cadence Verilog and Simulation, US Navy Leadership Responsibility and Management.
California (B General Building Contractor & C-10 - California Electrician License)

PROFESSIONAL EXPERIENCE

DTC CONSTRUCTION INC
Project Manager (January 2004 -- October 2007)

o Worked closely with customers and supplies. Duties would include to negotiate prices, bind customer to sign contracts, and offered technical expertise building perspectives and building applications. Conducted and managed the construction process, ensured the works worked effectively from rough to finish. Ensured and checked the company qualifications, customers' demands. Conducted and checked Commercial & Residential electrical (New & Remodel) wiring, installation and upgrading. Calculated load, read blue print, and ensured to meet the requirement of California Title 24 of Energy Conservation.

LSI LOGIC CORP.
Design Test Engineer (August 2002 -- September 2003)
Design Verification Engineer (June 2001 -- April 2002)

o Experience in Synopsys', Mentor Graphic's, and Cadence's design-for-simulation tools such as VCS, ModelSim, Verilog-XL, and NC-Verilog. Duties would include to qualifying these new CAD tool releases, tracking bugs, resolving issues, updating simulation applications, and providing training materials to design center engineers.

o Provided the technical consulting expertise in the area of simulation, simulation methodology (Verilog, VHDL, and mixed-language), from RTL designs to netlist (pre, post silicon) designs. Duties would include to analyzing, debugging, testing, and processing failed simulation issues. Defined and developed tests and regression methodologies for simulation of verification flows. Worked with different design groups to resolve and shared experience with simulation purposes.

o Developed, generated, tested, and updated regression test suites for tracking bugs, design library with timing flows, and comparing simulation mismatches, LSI's simulation methodology issues. Duties would include but not limited to consult and work closely with design center engineers, LSI's customers to resolve fail-simulation design issues, design simulation mismatches.

THESEUS LOGIC
Methodology and Development Engineer (April 1998 -- May 2001)

o Developed NCL (Null Convention Logic) VHDL simulation flow methodologies for Theseus' engineers and limited customers. Duties would include to implementing, developing, and enhancing NCL-VHDL library packages that would run from RTL to Component Levels. Ensuring the correctness NCL-VHDL methodology simulation issues, taken from RTL design to design netlist file simulations.

o Experience in Mentor Graphic's ModelSim VHDL simulation tool and Synopsys' Design Analyzer tool. Duties would include to developing regression NCL-VHDL simulation test suites to track bugs, resolving difference technical writing between standard VHDL and NCL-VHDL coding styles. Using synthesis tool to verify the netlist design-mapping methodology flows. These issues would include checking the redundant gate-mapping, incorrectness gate-mapping, logic redundancies,

o Provided internal engineers with the NCL-VHDL technical expertise in the area of simulation. Duties would include to work with circuit engineers, timing closure engineers, software developing groups, and NCL synthesis Methodology engineers to verify, resolve design issues with NCL technology and methodology.

UNITED STATE NAVY
Electrician Mate (April 1993 -- April 2001)

o Maintained and repaired ship circuit boards, breakers, electrical system controls. Blocked and braced weapons during transportation.

SAN JOSE STATE UNIVERSITY
Digital Logic Instructor and Matlab Instructor (August 1997 -- April 1999)

o Conducted Labs and prepared lab lectures. Duties would include helping student in writing and applying Matlab to their home work perspectives. Also, prepared lectures for engineer students in the introduction of digital logic and implement digital circuitry from home work designs, and class design assignments.

GENERAL DYNAMICS
Assistant Engineer (August 1992 -- July 1993)

o Tested and collected data for the integrated ATS Tests for the SINGARS Remote Switch module, SINGARS Smart Battery. Tested and debugged the coded test software to test the SINGARS RF section.

Certifications
See above


You must be logged in and have a current resume access subscription. Login or Register »

View all resumes in US-CA »

View other Verification & Development Engineer resumes, Tester / QA resumes