Primary Skills
ASIC/FPGA design with VHD/ Verilog
testing with LabView, o-scopes, logic analyzers, spectrum analyzers, and DMMs
Location
US-CA-San Jose (will consider relocating)
Posted
Apr-12-07
RESUME DETAILS
Experience -Test Engineer, DataSoft Corp.; Scottsdale, AZ -- April 2006 -- present --Wrote documentation outlining test plan to meet government requirements for software defined radio --Developed LabView control programs to test software defined radio requirements
-Associate Member of Technical Staff, Comtech EF Data; Tempe, AZ -- 2004-2006 --Developed and tested data interface option cards designed for satellite modems --Tested and evaluated modem components under development by other engineers --Investigated and fixed bugs reported by customers in previously released products --Reason for leaving: Position was eliminated during a company-wide reorganization.
Projects Completed -Gigabit Ethernet (GigE) Interface Design --Updated layout of existing design for better signal integrity and optimized control interface --Ported revised schematic to a separate base unit line utilizing a radically different data interface from the original unit --Revised the FPGA code of both designs to implement new additional functionality and improve timing characteristics
-High-Speed Serial Interface (HSSI) Design --Developed floor plan for HSSI schematic from basic specification of functionality, including basic block diagram and identification of specialized IC's to be used to simplify the design --Designed complete FPGA-based schematic in Orcad CIS --Programmed and simulated FPGA code in VHDL to implement data receiving, buffering, and transport across clock domains, as well as various error reporting and redundancy protocols --Prepared and executed comprehensive Design Verification Test to ensure correct functionality of basic design and correct timing and voltage levels of interconnect circuitry
Education Master of Science in Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, PA - May 2003
Bachelor of Science in Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, PA -- December 2002
Skills -VHDL and Verilog programming and simulation -FPGA design synthesis and implementation with Synplicity Synplify and Xilinx ISE -Schematic design with Orcad CIS -C/C++ programming; Perl scripting -Circuit analysis using oscilloscopes, logic analyzers, spectrum analyzers, digital multi-meters -Windows (3.1x, '9x, 2000, NT, XP); MacOS X; UNIX; LINUX -Text editing and layout using Microsoft Office Suite, Quark Xpress, Adobe PageMaker, Adobe -Photoshop, Adobe Acrobat -Conversant in German -Member: IEEE
Certifications
See above
CONTACT DETAILS
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