System/Alogrithmic Modeler and Digital Designer Resume

Title
System/Alogrithmic Modeler and Digital Designer

Primary Skills
C/C++, Matlab, SystemC, VHDL, Verilog, Perl, Python

Location
US-CA-San Diego (will consider relocating)

Posted
Mar-03-09

SUMMARY

Accomplished Systems Design Engineer with expertise in the areas of modeling, performance analysis and implementation with targeted focus on design re-use resulting in productive cross-group collaboration. Thorough implementation level knowledge in the field of Channel Coding and Processor Design allows for delivery of efficient and creative modeling techniques. Unique combination of skills in Architecture Modeling, Design and Verification Support can translate customer requirements into end-user products.

SKILLS

* Programming Languages & Operating Systems
o Modeling: Matlab w/ MEX support, C/C++, SystemC, XML(C++)
o RTL: VHDL, Verilog
o Scripting: Perl, Shell, TCL, Python
o Other Languages: Java, ASP, Pascal, Basic
o OS: Linux, Unix, Windows

* Design & Development Tools
o Architectural/u-Architectural Exploration: CatapultC, System Studio
o Synthesis: Synopsys Design Compiler
o Static Timing Analysis: Synopsys PrimeTime
o Power Analysis: Power Compiler, PrimePower
o Simulators: ModelSim, SimVision, Debussy, NCSim, ARM SDT Toolkit
o Debuggers: DDD, GDB, Microsoft Visual C++
o Design Capture: Cadence OrCAD
o Project/Data Management: CVS, Synchronicity, Bugzilla
o Documentation: Microsoft Office, Visio, FrameMaker

* Instruction Set Architectures (ISA)
o ARMv5
o MIPS

* Areas of Special Interest
o Read/Write Channels
o Processor Design
o Systems Design
o Digital Signal Processing

PATENTS

Method and Apparatus for Computing Incremental Checksum

EDUCATION

Bachelor of Science, Computer Engineering
University of California, San Diego
PROFESSIONAL EXPERIENCE

STMicroelectronics 2000 -- 2008
A Global Semiconductor company with a diverse product portfolio in all market segments including Communications, Consumer, Industrial, Computer and Automotive.

Design Architecture Staff Engineer (2006 -- 2008)
Data Storage Division -- Architecture
* Unified Matlab/C++ modeling environment enabling a common platform for architectural analysis and verification support.
* Enabled Matlab MEX interface support for effortless extraction of vital simulation data needed to evaluate algorithms and its effectiveness on the overall system.
* Collaborated extensively with verification team providing full support for front-end formal verification promoting design re-use.
* Delivered comprehensive customer support for higher flexibility as well as IP protection by utilizing XML support in a black-box simulation platform.
* Implemented both generic and bleeding-edge LDPC algorithms for high-throughput simulations and performance analysis.
* Spear-headed performance analysis of multiple variations of Interleavers in an Iterative Channel.

Design Engineer IV (2005 -- 2006)
Data Storage Division -- Implementation
* Developed parameterized RTL of Systematic Decoder for high-speed ASIC which was also ported onto FPGA for thorough verification and confirmation of its performances.
* Fix-point analysis and implementation of cycle-accurate C++ model for the Systematic Decoder providing a common simulation and verification platform.
* Modeled Front-End Streaming Unit (FESU) in SystemC for formal verification.
* Implemented RTL for the Write Path in VHDL overcoming challenges of multi-clock synchronization.
* Initiated FESU block-level Verification Test Plan exercising both functional and code coverage to ensure high formal verification standards.
* Validated various specifications of FESU using SystemC Co-simulation techniques for earlier feedback to block-level designer.
* Implemented data flow model using SystemC TLM concepts for evaluating multiple system-level memories.
* Completed preliminary work of porting C++ code for Systematic Decoder onto FPGA using CatapultC for fast deployment of performance analysis.

Design Engineer IV (2003 -- 2005)
Advance Computing -- VLIW Core
* Orchestrated and formalized design, implementation and verification flows using proprietary GDMS and CHT tools for fast, consistent company-wide deployment of the complete environment.
* Analyzed and provided feedback to designers on power characteristics within the embedded VLIW core using PrimePower and Power Compiler.
* Automated the flow of extracting relevant power characteristics information from PrimePower reports into an XML database using Perl.
* Formalized the methodology of further utilizing XML database for visual perspective on Architectural/u-Architectural trade-offs.

Design Engineer III (2000 -- 2003)
Advance Computing -- Super-scalar Processor Core
* Spear-headed the ISS development of Spock ISA by extensively collaborating with a team based in France paving the start of an eminent project focused on new trending design methodologies.
* Developed synthesizable, cycle-accurate, platform-based, multi-threaded, super-scalar processor design leveraging a subset of SystemC language and fostering to the new Spock ISA.
* Designed and synthesized various pipeline stages of the processor including decode, i-shelf and implementation level techniques such as score-boarding and micro-coding.
* Co-implemented Dynamic Branch Prediction using the bimodal scheme
* Verified the correctness of SystemC synthesis by co-simulating SystemC and Verilog blocks together.
* Managed and validated functional bugs by closely collaborating with all members of the team.
* Assembled efficient Perl scripts for end-of-day smoke test on EEMBC verification test suite.
* Managed complete revision tracking of the processor design and platform build distribution across other groups promoting concurrent development.

Tempest Microsystems, La Jolla, CA 1999
A provider of video solutions offering its technology in various market segments including Finance, Education, Enterprise, Homeland Security and Retail.

Hardware Engineer
* Captured and verified designs for Gigabit Ethernet Card and Video/Audio Encoder/Decoder.
* Proficient in OrCAD 9.1, verifying designs via use of netlist, generating bill of materials (BOM) and ordering parts for the daughter cards.

STMicroelectronics, San Diego, CA 1998
Intern Hardware Engineer
* Coordinated effort with team members for generating files for pmon pins.
* Responsible for documentation of Probe Mode and Host Test/Debug Ports.

Hewlett Packard, Rancho Bernardo, CA 1997
A Global technology company offering wide range of consumer products and services from digital photography to computing and home printing.

Software Test Developer and Tester
* Developed automated generated tests for verifying all functional aspects of Lanai Software Platform.
* Tested functional components of a multi-function printer as well as logging the encountered defects into Lotus Notes.

Certifications
See above


You must be logged in and have a current resume access subscription. Login or Register »

Resumes in San Diego, CA | Resumes in California

View other System/Alogrithmic Modeler and Digital Designer resumes, Programmer / Developer resumes