Resume of Sr Level Design Verification Engineer

Title
Sr Level Design Verification Engineer

Primary Skills
Over 22 years of digital logic design, simulation, and verification in computer graphics, networking, telecom industries

Location
US-FL-Oviedo

Posted
May-25-07

Professional Summary

- Over 22 years of digital logic design, simulation, and verification in the
computer graphics, networking, and telecommunication industries

- Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), and System design, architecture, verification and test including JTAG, SONET, IDE/ATAPI, and other proprietary protocols

- Design tool and process improvement, automation, support, and training

- Proficiencies: Verilog HDL (XL, NC, VCS, Polaris), VHDL, Vera, C/C++, FORTRAN, UNIX, Linux, Solaris, Windows OS, VMS, Cadence, Compass, MS Office, Matlab, UNIX C-shell and utilities

Intelliform Corp. experience:

October 2006 to February 2007 FPGA Design and Verification Contract for
Northrop Grumman Corp. - Design and verification of a hardware based real-time image registration processor based on high-level image processing algorithms that was targeted for implementation in an FPGA using VHDL. Developed FPGA hardware architecture based on Matlab implementation of the registration algorithms, and examined the impact of using available fixed-point DSP elements within the FPGA on calculation accuracy. Also supported hardware bring-up and debug of the subsystem board containing the FPGA, microprocessor, and support logic.

April 2006 to October 2006 Verification Contract for Qualcomm - Contributed to the verification effort on an advanced cell phone processor chip consisting of various internal IP cores and external peripherals. Worked primarily on the Top Level Mode Mux (TLMM) block that controlled over 170 general-purpose I/O pin assignments and the configuration for various test modes. Created and updated TLMM Software document to define GPIO assignments, and ran custom scripts to create associated Vera environment data. Created and updated TLMM test plan document. Created and updated TLMM block level tests. Identified various hardware bugs and simulation environment problems.

August 2003 to February 2006 Design and Verification Contract for Intellon -
Contributed to various aspects of a multi-phase project: converted cycle-based C code to VHDL for a Xilinx FPGA-based prototype design used to demonstrate and validate design concepts in the Home Plug AV standards submission for powerline based communications; supported simulation and verification of the design as well as FPGA prototype hardware testing; transitioned into the documentation, design, and verification of various hardware modules using Verilog in the ASIC implementation of the device from system design to tape-out; supported regression simulations and automatic model checking via PLI code and hardware accurate C algorithms; supported FPGA synthesis and downloading of device for partial ASIC emulation and development of C test code for in-house ASIC testing
and initial chip sorting; supported other software/firmware development for the device.

November 2001 to August 2002 Development Contract for Sega - Designed and implemented an FPGA and Intellectual Property (IP) for an ASIC to integrate Microsoft's Xbox with Sega's Arcade data storage subsystem. Accomplished all design aspects from system design through prototype test. Design and verification using Verilog. Implemented the design on Altera FPGA using Quartus software. Accomplished testing with Xbox Development kit and Intelliform's test equipment (HP Logic Analyzer and Tektronix Digital Storage Oscilloscope).

March 2000 to May 2001 Verification Support Contract for Nortel Networks -
Contributed to the verification team effort to simulate and verify a
sophisticated queue management ASIC used in multi-service switch product for the telecommunications industry. Created and reviewed conformance test plans. Developed simulation and test support environment, and wrote test benches based on the conformance test plans. Used Vera to simulate the design on Sun workstations and Linux PCs. Identified several design bugs and worked with ASIC designers to correct and re-verify the ASIC. Maintained all the test benches and test environment code using revision control system.

October 1999 to January 2000 Verification Support Contract for Fujitsu Network
Communications, Inc. - Contributed to the verification team effort to simulate
and verify 2 ASICs used in a 10-gigabit add/drop multiplexor proof-of- concept product being delivered on a tight schedule. Developed and documented directed tests using Verilog and VCS running on Sun workstations, and simulated the ASICs at the system level. Identified several design bugs and worked with the ASIC designers to correct and re-simulate the design.

November 1998 to July 1999 Verification Support Contract for Nortel Networks - Contributed to the verification team effort to simulate and verify an ASIC used in a terabit switch router product for the telecommunications industry. Worked closely with the ASIC designer to verify RTL modules at both the sub-system and system level by developing functional simulation models used in place of RTL code. Simulated the design using Vera running on Sun workstations. Identified design bugs and worked with the designer to correct and re-verify the design.

April 1998 to June 1998 Design, Verification, and Integration Support Contract
for Network Peripherals, Inc. - Provided ASIC design, verification, and
integration support for ASIC designs being used in a gigabit Ethernet product.
Worked in conjunction with the design team to incorporate top-level testing
schemes into the ASIC as well as verifying the built-in test functions. Also
set up a revision control system for ASIC design data.

June 1997 to January 1998 ASIC Design & Verification Contract for Alcatel -
Contributed to the design and verification team effort to create and test the
statistics gathering and computation module for an ASIC used in a SONET Line Multiplexor product. Designed modules using Verilog written at the RTL level. Wrote test benches using Verilog and VCS to simulate and verify module designs on Sun workstations.

July 1996 to December 1996 Digital Design & Verification Contract for IBM
Research & Development - Provided design and verification support for the
digital logic portion of a small, passively powered Radio Frequency
Identification (RFID) device. Worked closely with a large team of engineers
from various disciplines to transition the device from an R&D project into a
commercial product. Developed Verilog test benches for regression testing,
vendor test vector generation, and also in-house test vector generation used by HP test pattern generators. Provided test support for prototype devices prior to device packaging using wafer probe test fixture and also after device
packaging.

GE Aerospace / Lockheed Martin / Real 3D experience highlights:

Led a team of four in the development of a Texturing ASIC for use in the
entertainment industry from initial conceptual design through prototype
hardware testing. The ASIC contained over 1,000,000 transistors with
specialized DRAM and JTAG interfaces. Partitioned the design into top-level
modules, directed development and implementation of the modules and Verilog test benches for each. Verified RTL module functionality by comparisons with C language algorithms. Performed ASIC level integration as well as system level (multi-ASIC) integration support. Provided timing verification and test vectors for vendor sign-off. Overcame a significant performance challenge to attain system-operating speed with minimal overhead in the DRAM controller. Received a Managerial award for this effort.

Developed and integrated a real-time, computer graphics system for use in the entertainment industry. Developed Verilog RTL module designs and verified against C language algorithms. Performed ASIC integration as well as functional and timing verification. Developed Verilog test benches to support vendor test vector support. Provided on-site system test and debug support for the customer. The company sold more than two times the number of systems that marketing projections predicted. Received a Managerial award for this effort.

Developed and integrated a three-board system containing about 1000 electronic parts. This system formed the front-end to the geometry processor portion of a major Aerospace real-time, computer graphics system. Assisted firmware and software development team and produced numerous software functions for testing and debugging.

Saved GE Aerospace over $50,000 and two months of schedule delay by identifying a serious flaw in an ASIC during a detailed review process. Took over the design effort to correct and release the design. The ASIC worked correctly on the first pass.

Provided critical engineering support for design tool usage including training,
problem resolution, evaluation, and development of internal tools. Led to a
90% first pass success rate with ASIC's and a 75% reduction in system test
time.

Employment History
1996 - Present: Sr. Staff Engineer, Intelliform Corp.
1984 - 1996: Engineer - Sr. Design Engineer, GE Aerospace - Real 3D
(Lockheed Martin)

Education
BS Electrical Engineering, 1984 from Florida Institute of Technology; Graduated with Honors
BS Physics, 1984 from Jacksonville University; Graduated Magna Cum Laude

References available upon request

Certifications
See above


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