Job Details: STAFF DIGITAL FPGA/ASIC DESIGN ENGINEER
| Job Title: | STAFF DIGITAL FPGA/ASIC DESIGN ENGINEER |
| Company: | IGI |
| Position Type: | Contract |
| Pay Rate: | doe |
| Date Posted: | Sep-17-08 |
The Staff Digital FPGA/ASIC Design Engineer will be responsible for requirements analysis and derivation of requirements to a design architecture and physical device implementation.
• Create requirement documents and complete verification plans for FPGA/ASIC designs.
• Perform architectural trades from system level, to box level, to board level, to ASIC and or FPGA level design.
• Once requirements analysis has been completed and the requirements have been released candidate will design implementations at the system, box, board and ASIC (or FPGA) level design.
• This assignment involves the development of FPGA/ASIC requirements, RTL code, and simulation testbenches using VHDL.
• The architect of the design and implementation must be such that it meets the total dose and SEE environment required by the product. This architecture must be technology independent such that the design can be targeted to multiple different end item technologies.
• Responsible for requirement verification on the product through simulation, analysis, test, inspection and must prepare the engineering documentation required to illustrate design closure.
Additional Desired Qualifications:
• Must be a self starter and have demonstrated success in leading complex chip designs from concept through production.
Education Required:
• BSEE required
Experience Required:
• 12+ years experience in the specification and design of digital gate arrays, FPGAs and programmable logic devices.
• 10+ years VHDL design experience required.
• Experience with ASIC test insertion including ATPG, Vih/Vil, JTAG, MBIST, LBIST and designing technology independent architecture for test insertion.
• Experience with Space applications, static timing analysis, behavioral VHDL modeling, digital signal processing, built-in-test software development, and leveraging system algorithm modeling results to compose VHDL test benches is highly desirable.
• Experience developing technology independent solutions with multiple ASIC foundries. Experience with BAE, Honeywell and Aeroflex toolkits desirable.
Other Requirements (security clearance, US citizen, etc)
| Location: [rss] | US-NY-Rochester |
| Telecommute: | No (Onsite Position) |
| Contact Name: | Fern Piraino |
| Contact Phone: | 585-385-0610 x 207 |
| Contact Email: | fpiraino@igius.com |
Principals only. Recruiters, please do not contact this job poster.
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