Job Details: ASIC Verification Engineer
| Job Title: | ASIC Verification Engineer |
| Job ID: | ASICVERI |
| Company: | Yoh Engineering and IT |
| Position Type: | Permanent |
| Pay Rate: | 90,000 - 120,000 |
| Skills: | ASIC Verification, FPGA, C, C++, TCL, Perl |
| Date Posted: | Aug-06-08 |
Our client was conceived in April of 2002 by an international team of engineers and scientists from academia and industry with established backgrounds in processor architecture, compiler design and digital video/still imaging. They have developed a highly differentiated solution to address this problem of accelerating change and chaos. By revisiting and revising previous video and media processor architecture mindsets, the our client has realized that near-optimal performance and power efficiency can be attained, even for a purely programmable processor.
Our client brings to market for the first time a fully programmable device that can compete directly with fixed function ASIC solutions, in terms of performance and cost. This value proposition provides the opportunity for our client to build leading market share in the highly evolving and growing Digital Television and Multi-media market
Senior Design Verification Engineer
Location: Sunnyvale, CA
Reporting to the Hardware Director, the successful candidate is responsible for all aspects of chip verification and bring up.
Required skills:
• MUST HAVE 8+ years experience in ASIC/IC design and STRONG design verification experience
• Experience with post silicon verification
• Working knowledge of all aspects of prototype verification, both in the lab and on the test floor
• A technology background including CPU, digital video processing, and digital audio processing
• MUST have a strong background in ASIC
• Previous design verification and current hands-on capabilities
• A strong knowledge of ASIC design and manufacturing test methods
• BSEE or equivalent (MSEE preferred) or equivalent work experience
• Experience in DFT
• MUST be proficient in utilization of Unix and understanding of Unix utilities
• Excellent communication skills and ability to work effectively with others
• FPGA or hardware emulation experience
• Programming experience with TCL, Perl, C, C++
Duties Include:
• Perform architecture modeling in C or equivalent
• Create an RTL simulation environment from scratch that will accommodate third party IP
• Write design verification plans, directed tests, and regression suites
• Implement advanced verification techniques such as directed random testing and formal verification
• Measure test coverage
• Debug RTL and fault isolation
• Perform Test insertion and ATPG
• Develop simulations for generating functional test vectors to support ATE production testing
• Test prototypes
| Location: [rss] | US-CA-Sunnyvale |
| Telecommute: | No (Onsite Position) |
| Contact Name: | Cris Domingo |
| Contact Phone: | 408-654-9192 Xt 221 |
| Contact Email: | cris.domingo@yoh.com |
| URL: | http://www.yoh.com |
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Contact Comments:
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| Please email me your resume in MSWord format, prior to calling. | |
Principals only. Recruiters, please do not contact this job poster.
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